Libero IDE Quick Start Guide for Software v8.4
Introduction
The Libero IDE Quick Start Guide for Software v8.4 contains information for using the Libero® Integrated Design Environment (IDE) software to create designs for, and program, Actel devices.
This manual includes information about the Libero IDE software, which allows you to generate and/or import a netlist generated from a third-party CAE tool, perform pre-synthesis simulation, synthesize your design, place-and-route the design, run physical synthesis, perform static timing analysis, extract timing information, estimate power consumption, and generate a programming file to program an Actel FPGA.
This manual also refers to other Actel documents that contain additional information, including CAE software interface guides and simulation guides with specific information about using CAE tools with the Libero IDE.
Document Organization
The Libero IDE Quick Start Guide for Software v8.4 is divided into the following chapters:
Chapter 1 – Libero IDE Overview gives an overview of the programs contained in the Designer software.
Chapter 2 – Actel Design Flows illustrates and describes the design flow for creating Actel designs using the Designer software and third-party CAE tools.
Chapter 3 – Quick Start Tutorial illustrates a basic VHDL and Verilog design for the AGL Evaluation Board targeted at the Actel IGLOO family.
Appendix A – Product Support provides information about contacting Actel for customer and technical support.
Document Assumptions
- The information in this manual is based on the following assumptions:
- You have installed the Libero IDE software.
- You are familiar with PCs and Windows operating environments.
- You are familiar with FPGA architecture and FPGA design software.
- You are familiar with Libero IDE software and have prior experience with the IGLOO family.
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